In a microprogrammed processor, each instruction is executed by accessing a subroutine of elemental instructions, each of the instructions being called a micro-order. When the sequence of micro-orders for a given instruction is completed, the processor branches to a subroutine (fetch microprogram) which causes the next instruction to be fetched. The sequence of micro-orders making up each subroutine is called a microprogram, there being a separate microprogram associated with each instruction.
An instruction generally consists of two parts, an operation code and an operand address. In some machines, however, the operand address may be utilized in different ways in order to obtain the effective operand of the instruction depending on an addressing mode of the instruction. The addressing mode of the instruction is indicated by the operation code, normally being indicated by an address mode tag which is formed from the least significant bits (LSBs) of the operation code. The number of bits which are utilized for the tag will depend on the number of different address modes available in the processor. For example, for a system having up to eight different address modes the tag would be formed of the three LSBs of the operation code.
While a given processor may have any one of a variety of different address modes, the following is a list of typical address modes in a microprogrammed processor:
1. Direct Mode-a two word instruction where the second word contains the LSBs of the address where the effective operand is stored, the most significant bits (MSBs) of the address being the sector address presently stored in the processor program counter.
2. Direct Mode Zero Sector-same as 1 above except that the address in the second word is in the Zero (first) sector of memory.
3. Indirect Mode-same as 1 above except that the memory location indicated by the address in the second word contains an address where the effective operand is stored rather than the operand itself.
4. Indirect Mode Zero Sector-same as 3 above except that the address in the second word is located in the Zero (first) sector of the memory.
5. Immediate Mode-a two word instruction where the second word contains the effective operand.
6. Single Word Mode-this is a one word instruction which does not have an effective operand (for example increment accumulator).
7. Triple Word Mode-this is a three word instruction where the second and third words contain the total operand address. (i.e. both the sector address and the address within the sector).
Heretofore, at least four different methods have been utilized for finding the effective operand from the address mode tag and instruction operand. These methods have been:
1. Including the addressing mode phase of the fetch into the execution phase of each instruction. This requires that a set of address mode routines be provided for each operation code microprogram with the microprogram being entered at the beginning of the appropriate address mode routine associated with the instruction operation code microprogram, and there being a branch from the end of each address mode routine into the operation code portion of the microprogram.
2. Breaking a single instruction into several instructions, each one representing a different addressing mode. In this instance, there is a separate microprogram for each operation code in each of the different address modes in which it may be utilized. Thus, for example, if the processor has seven address modes, there would be seven microprograms stored for each operation code.
3. Same as 2 above except that all addressing modes are not included for all instructions.
4. Provide one central fetch routine and test and branch on the tag bits to obtain the proper address mode.
It is apparent that each of the techniques described above has certain limitations. Methods 1 and 2, (particularly method 2) cause a significant increase in the size requirement for the microprogram memory. Method 3 also results in an increase in the memory requirement on the microprogram memory and has the further disadvantage of diminishing the flexibility of the processor. While method 4 does not increase the microprogram memory requirements, and does provide complete flexibility, the requirement of successive tests and branch instructions for up to three encoded tag bits results in a number of microprogram memory cycles being required to select the proper address mode for each instruction. This significantly reduces the processor's speed and capacity.
A need thus exists for a method and apparatus to perform the address mode determination and effective operand selection functions which method does not require an increase in the size of the microprogram memory, permits all addressing modes to be included for all instructions, thus providing complete processor flexibility, and which permits the address mode determination to be performed in no more than one microprogram instruction time.